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cy7c027v/027av/028v cy7c037av/038v 3.3 v 32k/64k x 16/18 dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06078 rev. *e revised october 14, 2011 features true dual-ported memory cells which allow simultaneous access of th e same memory location 32k x 16 organization (cy7c027v/027av [1] ) 64k x 16 organization (cy7c028v) 32k x 18 organization (cy7c037av) 64k x 18 organization (cy7c038v) 0.35 micron complementary metal oxide semiconductor (cmos) for optimum speed and power high speed access: 15, 20, and 25 ns low operating power active: i cc = 115 ma (typical) standby: i sb3 = 10 ? a (typical) fully asynchronous operation automatic power-down expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to- port communication separate upper-byte and lower-byte control dual chip enables pin select for master or slave commercial and industrial temperature ranges 100-pin pb-free thin quad plastic flatpack (tqfp) and 100-pin tqfp notes 1. cy7c027v, and cy7c027av are functionally identical. 2. i/o 8 ?i/o 15 for x16 devices; i/o 9 ?i/o 17 for x18 devices. 3. i/o 0 ?i/o 7 for x16 devices; i/o 0 ?i/o 8 for x18 devices. 4. a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices. 5. busy is an output in master mode and an input in slave mode. r/w l ce 0l ce 1l oe l i/o 8/9l ?i/o 15/17l i/o control address decode a 0l ?a 14/15l ce l oe l r/w l busy l i/o control ce l interrupt semaphore arbitration sem l int l m/s ub l lb l i/o 0l ?i/o 7/8l r/w r ce 0r ce 1r oe r i/o 8/9l ?i/o 15/17r ce r ub r lb r i/o 0l ?i/o 7/8r ub l lb l logic block diagram a 0l ?a 14/15l true dual-ported ram array a 0r ?a 14/15r ce r oe r r/w r busy r sem r int r ub r lb r address decode a 0r ?a 14/15r [2] [2] [3] [3] [4] [4] [5] [5] [4] [4] 15/16 8/9 8/9 15/16 8/9 8/9 15/16 15/16
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 2 of 22 contents pin configurations ........................................................... 3 pin configurations (continued) ........................................ 4 selection guide ................................................................ 4 pin definitions .................................................................. 5 architecture ...................................................................... 5 functional description ..................................................... 5 write operation ........................................................... 5 read operation ........................................................... 5 interrupts ..................................................................... 5 busy ............................................................................ 6 master/slave ............................................................... 6 semaphore operation ............ .............. .............. ......... 6 maximum ratings ............................................................. 7 operating range ............................................................... 7 electrical characteristics.................................................. 7 capacitance ...................................................................... 7 switching characteristics ................................................ 8 data retention mode ........................................................ 9 timing ................................................................................ 9 switching waveforms .................................................... 10 ordering information ...................................................... 17 32k x16 3.3 v asynchronous dual-port sram ........ 17 64k x16 3.3 v asynchronous dual-port sram ........ 17 32k x18 3.3 v asynchronous dual-port sram ........ 17 64k x18 3.3 v asynchronous dual-port sram ........ 17 ordering code definition .... ....................................... 18 package diagram ............................................................ 19 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc solutions ......................................................... 22
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 3 of 22 pin configurations figure 1. 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a9r a10r a11r a12r a13r a14r ubr nc lbr ce1r semr oer gnd nc a15r gnd r/wr gnd i/o15r i/o14r i/o13r i/o12r i/o11r i/o10r ce0r 58 57 56 55 54 53 52 51 cy7c027v/027av (32k x 16) a9l a10l a11l a12l a13l a14l ubl nc lbl ce1l seml oel gnd nc a15l vcc r/wl gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l ce0l 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l intl a1l nc gnd m/s a0r a1r a0l a2l busyr intr a2r a3r a4r a5r a6r a7r a8r busyl 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 nc i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c028v (64k x 16) [6] [6] note 6. this pin is nc for cy7c027v/027av.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 4 of 22 pin configurations (continued) figure 2. 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 a8r a9r a10r a11r a12r a13r ce0r a15r ubr semr r/wr gnd i/o17r lbr a14r gnd oer gnd i/o16r i/o15r i/o14r i/o13r i/o12r i/o11r ce1r 58 57 56 55 54 53 52 51 cy7c037av (32k x 18) a9l a10l a11l a12l a13l a14l ce1l lbl ce0l r/wl oel i/o17l i/o16l ubl a15l vcc gnd gnd i/o15l i/o14l i/o13l i/o12l i/o11l i/o10l seml 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 a8l a7l a6l a5l a4l a3l busyl a1l intl gnd vcc intr a0r a0l a2l m/s busyr a1r a2r a3r a4r a5r a6r a7r gnd 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 i/o10r i/o9r i/o8r i/o7r vcc i/o6r i/01r i/o4r i/o2r gnd i/o0l i/o2l i/o3l i/o3r i/o5r i/o1l gnd i/o4l i/o5l i/o6l i/o7l vcc i/o8l i/o9l i/o0r 33 32 31 30 29 28 27 26 cy7c038v (64k x 18) [7] [7] selection guide parameter -15 -20 -25 unit maximum access time 15 20 25 ns typical operating current 125 120 115 ma typical standby current for i sb1 (both ports ttl level) 35 35 30 ma typical standby current for i sb3 (both ports cmos level) 10 ? a 10 ? a10 ? a ? a note 7. this pin is nc for cy7c037av.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 5 of 22 architecture the cy7c027v/027av/028v and cy7037av/038v consist of an array of 32k and 64k words of 16 and 18 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description the cy7c027v/027av/028v and cy7037av/038v are low power cmos 32k, 64k x 16/18 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as stand-alone 16/18-bit dual-port static rams or mult iple devices can be combined to function as a 32/36-bit or wider master/slave dual-port static ram. an m/s pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multipro cessor designs, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the sa me location currently be ing accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c027v/027av/028v and cy7037av/038v are available in 100-pin thin quad plastic flatpacks (tqfp). write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 7 ) or the ce pin (see figure 8 ). required inputs for non-contention operations are summarized in ta b l e 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (7fff for the cy7c027v/037av/027av, ffff for the cy7c028v/38v) is the mailbox for the right port and the second-highest memory location (7ffe for the cy7c027v/027av/037av, fffe for the cy7c028v/38v) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. pin definitions left port right port description ce 0l , ce 1l ce 0 r , ce 1r chip enable (ce is low when ce 0 ? v il and ce 1 ?? v ih ) r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 15l a 0r ?a 15r address (a 0 ?a 14 for 32k; a 0 ?a 15 for 64k devices) i/o 0l ?i/o 17l i/o 0r ?i/o 17r data bus input/output (i/o 0 ?i/o 15 for x16 devices; i/o 0 ?i/o 17 for x18) sem l sem r semaphore enable ub l ub r upper byte select (i/o 8 ?i/o 15 for x16 devices; i/o 9 ?i/o 17 for x18 devices) lb l lb r lower byte select (i/o 0 ?i/o 7 for x16 devices; i/o 0 ?i/o 8 for x18 devices) int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 6 of 22 each port can read the other po rt?s mailbox without resetting the interrupt. the active state of th e busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts a nd their interaction with busy are summarized in ta b l e 2 . busy the cy7c027v/027av/028v and cy7037av/038v provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location, but it is not predictable which port gets that permission. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this allows the device to interface to a master device with no external components. writing to slave devices must be de layed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a wr ite cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c027v/027av/028v and cy7037av/038v provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports.the state of the semaphore indicates that a resour ce is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relin- quished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0?2 represents the semaphore address. oe and r/w are used in the same manne r as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. ta b l e 3 shows sample semaphore operations. when reading a semaphore, all sixteen/eighteen data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 7 of 22 maximum ratings exceeding maximum ratings may s horten the useful life of the device. user guidelines are not tested. storage temperature ................................ ?65 ? c to +150 ? c ambient temperature with power applied ........................................... ?55 ? c to +125 ? c supply voltage to ground potenti al ...............?0.5 v to +4.6 v dc voltage applied to outputs in high-z state........................... ?0.5 v to v cc +0.5 v dc input voltage [8] ................................. ?0.5 v to v cc +0.5 v output current into outputs (low) .............................. 20 ma static discharge voltage........... ............................... > 1100 v latch-up current .................................................... > 200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3 v ? 300 mv industrial [9] ?40 ? c to +85 ? c 3.3 v ? 300 mv electrical characteristics over the operating range parameter description cy7c027v/027av/028v/cy7c037av/cy7c038v unit -15 -20 -25 min typ max min typ max min typ max v oh output high voltage (v cc =min., i oh = ?4.0 ma) 2.4 ? 2.4 ? ? 2.4 ? ? v v ol output low voltage (v cc =min., i oh = +4.0 ma) ? 0.4 ? 0.4 ? 0.4 v v ih input high voltage 2.2 ? 2.2 ? 2.2 ? v v il input low voltage ? 0.8 ? 0.8 ? 0.8 v i ix input leakage current ? 55 ? 55 ? 55 ? a i oz output leakage current ?10 10 ?10 10 ?10 10 ? a i cc operating current (v cc =max. i out =0 ma) outputs disabled com?l. 125 185 ? 120 175 ? 115 165 ma ind. [9] ? 140 195 ? ma i sb1 standby current (both ports ttl level) ce l & ce r ? v ih , f=f max com?l. 35 50 35 45 30 40 ma ind. [9] ?4555 ?ma i sb2 standby current (one port ttl level) ce l | ce r ? v ih , f=f max com?l. 80 120 75 110 65 95 ma ind. [9] ?85120 ?ma i sb3 standby current (both ports cmos level) ce l & ce r ? v cc ? 0.2 v, f=0 com?l. 10 250 10 250 10 250 ? a ind. [9] ?10250 ? ? a i sb4 standby current (one port cmos level) ce l | ce r ? v ih , f=f max [10] com?l. 75 105 70 95 60 80 ma ind. [9] ?80105 ?ma capacitance [11] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 10 pf c out output capacitance 10 pf notes 8. pulse width < 20 ns. 9. industrial parts are available in cy7c028v and cy7c038v, cy7c027v/027av only. 10. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 11. tested initially and after any design or proc ess changes that may affect these parameters.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 8 of 22 figure 3. ac test loads and waveforms 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3 v output r2 = 435 ? c= 30 pf v th = 1.4 v output c= 30 pf (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3 v output c= 5pf r th = 250 ? ? ? including scope and jig) (used for t lz , t hz , t hzwe , & t lzwe switching characteristics over the operating range [12] parameter description cy7c027v/027av/028v/ cy7c037av/cy7c038v unit -15 -20 -25 min max min max min max read cycle t rc read cycle time 15 ? 20 ? 25 ? ns t aa address to data valid ? 15 ? 20 ? 25 ns t oha output hold from address change 3 ? 3 ? 3 ? ns t ace [13] ce low to data valid ? 15 ? 20 ? 25 ns t doe oe low to data valid ?10?12?13ns t lzoe [14, 15, 16] oe low to low z 3?3?3?ns t hzoe [14, 15, 16] oe high to high z ? 10 ? 12 ? 15 ns t lzce [14, 15, 16] ce low to low z 3 ? 3 ? 3 ? ns t hzce [14, 15, 16] ce high to high z ?10?12?15ns t pu [16] ce low to power-up 0 ? 0 ? 0 ? ns t pd [16] ce high to power-down ? 15 ? 20 ? 25 ns t abe [13] byte enable access time ? 15 ? 20 ? 25 ns write cycle t wc write cycle time 15 ? 20 ? 25 ? ns t sce [13] ce low to write end 12 ? 16 ? 20 ? ns t aw address valid to write end 12 ? 16 ? 20 ? ns t ha address hold from write end 0 ? 0 ? 0 ? ns t sa [13] address setup to write start 0 ? 0 ? 0 ? ns t pwe write pulse width 12?17?22? ns t sd data setup to write end 10?12?15? ns notes 12. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3.0 v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 13. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 14. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 15. test conditions used are load 2. 16. this parameter is guaranteed by design, but it is not produc tion tested. for information on port-to-port delay through ram c ells from writing port to reading port, refer to figure 11 .
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 9 of 22 data retention mode the cy7c027v/027av/028v and cy7037av/038v are de- signed with battery backup in mind. data retention voltage and supply current are guaranteed ov er temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2 v 2. ce must be kept between v cc ? 0.2 v and 70% of v cc during the power up and power down transitions 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (3.0 v) t hd data hold from write end 0 ? 0 ? 0 ? ns t hzwe [17, 18] r/w low to high z ? 10 ? 12 ? 15 ns t lzwe [17, 18] r/w high to low z 3 ? 3 ? 3 ? ns t wdd [21] write pulse to data delay ? 30 ? 40 ? 50 ns t ddd [21] write data valid to read data valid ? 25 ? 30 ? 35 ns busy timing [19] t bla busy low from address match ? 15 ? 20 ? 20 ns t bha busy high from address mismatch ? 15 ? 20 ? 20 ns t blc busy low from ce low ?15?20?20ns t bhc busy high from ce high ?15?16?17ns t ps port setup for priority 5 ? 5 ? 5 ? ns t wb r/w high after busy (slave) 0?0?0?ns t wh r/w high after busy high (slave) 13?15?17? ns t bdd [21] busy high to data valid ? 15 ? 20 ? 25 ns interrupt timing [19] t ins int set time ? 15 ? 20 ? 20 ns t inr int reset time ? 15 ? 20 ? 20 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10?10?12? ns t swrd sem flag write to read time 5 ? 5 ? 5 ? ns t sps sem flag contention window 5 ? 5 ? 5 ? ns t saa sem address access time ? 15 ? 20 ? 25 ns switching characteristics over the operating range [12] (continued) parameter description cy7c027v/027av/028v/ cy7c037av/cy7c038v unit -15 -20 -25 min max min max min max timing parameter test conditions [22] max unit icc dr1 at vcc dr = 2 v 50 ? a data retention mode 3.0 v 3.0 v v cc ? ? 2.0 v v cc to v cc ? 0.2 v v cc ce t rc v ih notes 17. test conditions used are load 2 18. this parameter is guaranteed by design, but it is not production tested. for information on port-to-port delay through ram c ells from writing port to reading port, refer to figure 11 . 19. for information on port-to-port delay through ram cells from writing port to reading port, refer to figure 11 waveform. 20. test conditions used are load 1. 21. t bdd is a calculated parameter and is the greater of t wdd ?t pwe (actual) or t ddd ?t sd (actual). 22. ce = v cc , v in = gnd to v cc , t a = 25 ? c. this parameter is guaranteed but not tested.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 10 of 22 switching waveforms notes 23. r/w is high for read cycles. 24. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 25. oe = v il . 26. address valid prior to or coincident with ce transition low. 27. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha figure 4. read cycle no. 1 (either port address access) [23, 24, 25] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current figure 5. read cycle no. 2 (either port ce /oe access) [23, 26, 27] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce figure 6. read cycle no. 3 (either port) [23, 25, 26, 27]
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 11 of 22 notes 28. r/w must be high during all address transitions. 29. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 30. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 31. if oe is low during a r/w controlled write cycle, th e write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does no t apply and the write pulse can be as short as the specified t pwe . 32. to access ram, ce = v il , sem = v ih . 33. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 34. transition is measured ? 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and not 100% tested. 35. during this period, the i/o pins are in the out put state, and input signals must not be applied. 36. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe figure 7. write cycle no. 1: r/w controlled timing [28, 29, 30, 31] [34] [34] [31] [32,33] note 35 note 35 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa figure 8. write cycle no. 2: ce controlled timing [28, 29, 30, 36] [32,33]
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 12 of 22 notes 37. ce = high for the duration of the above timing (both write and read cycle). 38. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 39. semaphores are reset (available to both ports) at cycle start. 40. if t sps is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable . switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem 0 ?a 2 figure 9. semaphore read after write timing, either side [37] a match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r figure 10. timing diagra m of semaphore contention [38, 39, 40]
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 13 of 22 note 41. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l figure 11. timing diagram of read with busy (m/s =high) [41] t pwe r/w busy t wb t wh figure 12. write timing with busy input (m/s =low)
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 14 of 22 note 42. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy is asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r figure 13. busy timing diagram no. 1 (ce arbitration) [42] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: figure 14. busy timing diagram no. 2 (address arbitration) [42] left address valid first:
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 15 of 22 figure 15. interrupt timing diagrams notes 43. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 44. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write 7fff (ffff for cy7c028v/38v) t wc right side clears int r : t ha read 7fff t rc t inr write 7ffe (fffe for cy7c028v/38v) t wc right side sets int l : left side sets int r : left side clears int l : read 7ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (ffff for cy7c028v/38v) (fffe for cy7c028v/38v) [43] [44] [44] [44] [43] [44]
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 16 of 22 table 1. non-contending read/write inputs outputs ce r/w oe ub lb sem i/o 9 ? i/o 17 i/o 0 ? i/o 8 operation h x x x x h high z high z deselected: power-down x x x h h h high z high z deselected: power-down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) [45] left port right port function r/w l ce l oe l a 0 l ?14 l int l r/w r ce r oe r a 0r?14r int r set right int r flag l l x 7fff x x x x x l [47] reset right int r flagxxxxxxll7fffh [46] set left int l flag x x x x l [46] llx 7ffe x reset left int l flag x l l 7ffe h [47] xxx x x table 3. semaphore operation example function i/o 0 ? i/o 17 left i/o 0 ? i/o 17 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes 45. a 0l?15l and a 0r?15r ,ffff/fffe for the cy7c028v/038v. 46. if busy r =l, then no change. 47. if busy l =l, then no change.
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 17 of 22 ordering information 32k x16 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c027v-15axc a100 100-pin pb-free thin quad flat pack commercial cy7c027v-15axi a100 100-pin pb-free thin quad flat pack industrial 20 cy7c027v-20ac a100 100-pin thin quad flat pack commercial cy7c027v-20axc a100 100-pin pb-free thin quad flat pack commercial 25 cy7c027v-25ac a100 100-pin thin quad flat pack commercial cy7c027v-25axc a100 100-pin pb-free thin quad flat pack commercial CY7C027AV-25AXI a100 100-pin pb-fr ee thin quad flat pack industrial 64k x16 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 cy7c028v-15axc a100 100-pin pb-fr ee thin quad flat pack commercial cy7c028v-15axi a100 100-pin pb-free thin quad flat pack industrial 20 cy7c028v-20ac a100 100-pin thin quad flat pack commercial cy7c028v-20axc a100 100-pin pb-free thin quad flat pack commercial cy7c028v-20ai a100 100-pin thin quad flat pack industrial cy7c028v-20axi a100 100-pin pb-free thin quad flat pack industrial 25 cy7c028v-25ac a100 100-pin thin quad flat pack commercial cy7c028v-25axc a100 100-pin pb-free thin quad flat pack commercial 32k x18 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c037av-20axc a100 100-pin pb-free thin quad flat pack commercial 64k x18 3.3 v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 20 cy7c038v-20axi a100 100-pin pb-fr ee thin quad flat pack industrial
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 18 of 22 ordering code definition cy 7c 0x xx company id: cy = cypress 7c = dual port sram width: 02=x16 or 03=x18 operating range c = commercial i = industrial x depth: 7=32k or 8=64k ax package: a=tqfp speed grade : 15ns/20ns/25ns x x : pb free (rohs compliant) x x = v/av : 3.3 v
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 19 of 22 package diagram figure 16. 100-pin pb-free thin plastic quad flat pack (tqfp) a100 51-85048 *e
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 20 of 22 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory tqfp thin quad plastic flatpack symbol unit of measure c degree celsius mhz mega hertz a microamperes ma milliamperes mv millivolts ns nanoseconds ? ohms pf picofarad vvolts wwatts
cy7c027v/027av/028v cy7c037av/038v document #: 38-06078 rev. *e page 21 of 22 document history page document title: cy7c027v/027av/ cy7c028v/037av/038v 3.3 v 32k/64 k x 16/18 dual port static ram document number: 38-06078 rev. ecn no. orig. of change submission date description of change ** 237626 ydt 6/30/04 converted data sheet from old spec 38-00670 to conform with new data sheet. removed cross information from features section *a 259110 jhx see ecn added pb-free packaging information. *b 2623540 vkn/pyrs 12/17/08 added cy7c027vn, cy7c027av and cy7c037av parts updated ordering information table *c 2897217 rame 03/22/2010 updated ordering information updated package diagram *d 3093542 admu 11/25/2010 removed information on cy7c027vn and cy7c037v updated as per new template added acronyms and units of measure table added ordering code definition updated all footnotes *e 3403652 admu 10/14/2011 removed pruned part s cy7c027v-25ai, cy7c038v-20ai from ordering information updated package diagram .
document #: 38-06078 rev. *e revised october 14, 2011 page 22 of 22 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c027v/027av/028v cy7c037av/038v ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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